Updated on 2024/04/25

写真a

 
TAKAHASHI Toshihiko
 
Organization
Academic Assembly Institute of Science and Technology JOUHOU DENSHI KOUGAKU KEIRETU Associate Professor
Faculty of Engineering Department of Engineering Associate Professor
Title
Associate Professor
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Degree

  • 工学博士 ( 1991.3   東京工業大学 )

Research History

  • Niigata University   Faculty of Engineering Department of Engineering   Associate Professor

    2017.4

  • Niigata University   Faculty of Engineering Department of Information Engineering   Associate Professor

    2010.4

  • Niigata University   Graduate School of Science and Technology Electrical and Information Engineering   Associate Professor

    2010.4 - 2017.3

  • Niigata University   Graduate School of Science and Technology Information Science and Engineering   Associate Professor

    2004.4 - 2010.3

  • Niigata University   Faculty of Engineering   Lecturer

    1993.10 - 1995.3

  • Niigata University   Faculty of Engineering   Research Assistant

    1991.4 - 1993.9

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Professional Memberships

  • The Institute of Electrical and Electronics Engineers, Inc. (IEEE)

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  • INFORMATION PROCESSING SOCIETY OF JAPAN

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Committee Memberships

  • 電子情報通信学会   回路とシステム研究会 顧問  

    2017.5   

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    Committee type：Academic society

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  • 電子情報通信学会   回路とシステム研究会 委員長  

    2016.6 - 2017.5   

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    Committee type：Academic society

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  • 電子情報通信学会   回路とシステム研究会 副委員長  

    2015.6 - 2016.5   

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    Committee type：Academic society

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  • 電子情報通信学会   回路とシステム研究専門委員  

    2008.4 - 2014.5   

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    Committee type：Academic society

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  • 電子情報通信学会   2009年ソサイエティ大会実行委員  

    2007.12 - 2009.12   

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    Committee type：Academic society

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Papers

  • Enumerating z Sequences of k-ary Trees in Colexicogaphic Order Reviewed

    T. Takahashi, T. Aketagawa

    The 32nd International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2017).   2017.7

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    Language：English   Publishing type：Research paper (international conference proceedings)  

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  • On the Three-Dimensional Channel Routing Reviewed

    Satoshi Tayu, Toshihiko Takahashi, Eita Kobayashi, Shuichi Ueno

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E99A ( 10 )   1813 - 1821   2016.10

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    Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

    The 3-D channel routing is a fundamental problem on the physical design of 3-D integrated circuits. The 3-D channel is a 3-D grid G and the terminals are vertices of G located in the top and bottom layers. A net is a set of terminals to be connected. The objective of the 3-D channel routing problem is to connect the terminals in each net with a Steiner tree (wire) in G using as few layers as possible and as short wires as possible in such a way that wires for distinct nets are disjoint. This paper shows that the problem is intractable. We also show that a sparse set of v 2-terminal nets can be routed in a 3-D channel with O(root v) layers using wires of length O(root v).

    DOI： 10.1587/transfun.E99.A.1813

    Web of Science

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  • The simplest and smallest network on which the ford-fulkerson maximum flow procedure may fail to terminate Reviewed

    Toshihiko Takahashi

    Journal of Information Processing   24 ( 2 )   390 - 394   2016.3

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    Language：English   Publishing type：Research paper (scientific journal)   Publisher：Information Processing Society of Japan  

    Ford and Fulkerson’s labeling method is a classic algorithm for maximum network flows. The labeling method always terminates for networks whose edge capacities are integral (or, equivalently, rational). On the other hand, it might fail to terminate if networks have an edge with an irrational capacity. Ford and Fulkerson also gave an example of such networks on which the labeling method might fail to terminate. However, their example has 10 vertices and 48 edges and the flow augmentation is a little bit complicated. Simpler examples have been published in the past. In 1995, Zwick gave two networks with 6 vertices and 9 edges and one network with 6 vertices and 8 edges. The latter is the smallest, however, the calculation of the irrational capacity requires some effort. Thus, he called the former the simplest. In this paper, we show the simplest and smallest network in Zwick’s context. Moreover, the irrational edge capacity of our example can be arbitrarily assigned while those in the all previous examples are not. This suggests that many real-valued networks might fail to terminate.

    DOI： 10.2197/ipsjjip.24.390

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  • A Compact Code for Rectangular Drawings with Degree Four Vertices Reviewed

    Toshihiko Takahashi

    Journal of Information Processing   22 ( 4 )   634 - 637   2014.10

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    Language：English   Publishing type：Research paper (scientific journal)   Publisher：Information Processing Society of Japan  

    A subdivision of a rectangle into rectangular faces with horizontal and vertical line segments is called a rectangular drawing or floorplan. Several encodings of rectangular drawings have been published
    however, most of them deal with rectangular drawings without vertices of degree four. Recently, Saito and Nakano developed two compact encodings for general rectangular drawings, that is, which allows vertices of degree four. The two encodings respectively need 6f − 2n4 + 6 bits and 5f −5 bits for rectangular drawings with f inner faces and n4 degree four vertices. The best encoding of the two depends on the number of vertices of degree four, that is, the former is the better if 2n4 &gt
    f+11
    otherwise the latter is the better. In this paper, we propose a new encoding of general rectangular drawings with 5f− n4 − 6 bits for f ≥ 2, which is the most compact regardless of n4.

    DOI： 10.2197/ipsjjip.22.634

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  • Rectilinear Steiner arborescence問題の厳密解法における枝刈り規則について Invited Reviewed

    長瀬将行, 高橋俊彦

    電子情報通信学会論文誌A   J92-A ( 7 )   432 - 439   2013.7

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    Language：Japanese   Publishing type：Research paper (scientific journal)   Publisher：電子情報通信学会  

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  • A Compact Code for Rectangular Drawings with Degree Four Vertices Reviewed

    Toshihiko Takahashi

    第12回情報科学技術フォーラム(FIT2013)   RA-003   2013

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    Language：English   Publishing type：Research paper (other academic)   Publisher：情報処理学会  

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  • (3n-4)-bit Representation of Rectangular Partitions Reviewed

    Toshihiko Takahashi

    Proceeding of The 27th International Technical Conference o Circuits/Systems, Computers and Communications   2012.7

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  • スライス構造型フロアプランの列挙 Reviewed

    越前 俊一, 高橋 俊彦

    第25回 回路とシステム軽井沢ワークショップ論文集   196 - 201   2012.7

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  • On pruning rules in optmal algorithms for the minimum rectilinear Steiner arborescence problem III Reviewed

    M. Nagase, T.Takahashi

    The 24th Workshop on Circuits and Systems in Karuizawa   443 - 448   2011.7

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  • A (4n-4)-Bit Representation of a Rectangular Drawing or Floorplan Reviewed

    T. Takahashi, Fujimaki, Y. Inoue

    Lecture Notes in Computer Science, H.Q. Ngo (Ed.): COCOON 2009, LNCS 5609   47 - 55   2009.7

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    Language：English   Publishing type：Research paper (international conference proceedings)  

    DOI： 10.1007/978-3-642-02882-3_6

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  • An Asymptotic Estimate of the Numbers of Rectangular Drawings or Floorplans Reviewed

    R. Fujimaki, T. Takahashi

    Proc. 2009 IEEE International Symposium on Circuits and Systems (ISCAS2009)   856 - 859   2009.5

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    Language：English   Publishing type：Research paper (international conference proceedings)  

    DOI： 10.1109/ISCAS.2009.5117891

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  • Static binary search tree: An application to sub-crossbar problem for two-directional orthogonal rays Reviewed

    Toshihiko Takahashi

    The 22nd Workshop on Circuits and Systems in Karuizawa   506 - 509   2009.4

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  • Counting Rectangular Drawings or Floorplans in Polynomial Time Reviewed

    Youhei Inoue, Toshihiko Takahashi, Ryo Fujimaki

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E92A ( 4 )   1115 - 1120   2009.4

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    Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

    A subdivision of a rectangle into rectangular faces with horizontal and vertical line segments is called a rectangular drawing or floorplan. It has been an open problem to determine whether there exist a polynomial time algorithm for computing R(n). We affirmatively solve the problem, that is, we introduce an O(n(4))-time and O(n(3))-space algorithm for R(n). The algorithm is based on a recurrence for R(n), which is the main result of the paper. We also implement our algorithm and computed R(n) for n <= 3000.

    DOI： 10.1587/transfun.E92.A.1115

    Web of Science

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  • Fujimaki-Takahashi squeeze: Linear time construction of constraint graphs of floorplan for a given permutation Reviewed

    Toshihiko Takahashi, Ryo Fujimaki

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E91A ( 4 )   1071 - 1076   2008.4

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    Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

    A floorplan is a subdivision of a rectangle into rectangular faces with horizontal and vertical line segments. We call a floorplan room-to-room when adjacencies between rooms are considered. Fujimaki and Takahashi showed that any room-to-room floorplan can be represented as a permutation. In this paper, we give an O(n)-time algorithm that constructs the vertical and the horizontal constraint graphs of a floorplan for a given permutation under this representation.

    DOI： 10.1093/ietfec/e91-a.4.1071

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  • Fujimaki-Takahashi squeeze: Linear time construction of constraint graphs of floorplan for a given permutation Reviewed

    Toshihiko Takahashi, Ryo Fujimaki

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E91A ( 4 )   1071 - 1076   2008.4

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    A floorplan is a subdivision of a rectangle into rectangular faces with horizontal and vertical line segments. We call a floorplan room-to-room when adjacencies between rooms are considered. Fujimaki and Takahashi showed that any room-to-room floorplan can be represented as a permutation. In this paper, we give an O(n)-time algorithm that constructs the vertical and the horizontal constraint graphs of a floorplan for a given permutation under this representation.

    DOI： 10.1093/ietfec/e91-a.4.1071

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  • Counting rectangular drawings of floorplans in polynomial time Reviewed

    Y. Inoue, R.Fujimaki, T.Takahashi

    The 21st Workshop on Circuits and Systems in Karuizawa   653 - 658   2008.4

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    Language：Japanese   Publishing type：Research paper (conference, symposium, etc.)  

    CiNii Article

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  • Fujimaki-Takahashi Squeeze : Linear Time Construction of Constraint Graphs of Floorplan Reviewed

    T.Takahashi, R.Fujimaki

    The 20th Workshop on Circuits and Systems in Karuizawa   307 - 311   2007.4

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  • A surjective mapping from permutations to room-to-room floorplans Reviewed

    Ryo Fujimaki, Toshihiko Takahashi

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E90A ( 4 )   823 - 828   2007.4

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    Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

    A floorplan is a subdivision of a rectangle into rectangular faces with horizontal and vertical line segments. Heuristic search algorithms are used to find desired floorplans in applications, including sheet-cutting, scheduling, and VLSI layout design. Representation of floorplan is critical in floorplan algorithms, because it determines the solution space searched by floorplan algorithms. In this paper, we show a surjective mapping from permutations to room-to-room floorplans. This mapping gives us a simple representation of room-to-room floorplans.

    DOI： 10.1093/ietfec/e90-a.4.823

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  • A Mapping Between Permutation and Floorplan Including Room-Room Adjacency Reviewed

    R.Fujimaki, T.Takahashi

    The 19th Workshop on Circuits and Systems in Karuizawa   19   247 - 252   2006.4

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    Language：Japanese   Publishing type：Research paper (conference, symposium, etc.)  

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  • Linear Time Transformation from Baxter Permutations to Rectangular Partitions Reviewed

    T.Takahashi

    The1 8th Workshop on Circuits and Systems in Karuizawa   223 - 228   2005.4

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  • A New Algorithm for Optimal File Transfer on Path Networks Reviewed

    T.Takahashi, K.Hirabayashi

    Proc. The 2001 International Technical Conference on Circuits/Systems   1   324 - 326   2001.12

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  • 矩形パッキング問題における解空間の解析 Reviewed

    春多宏紀, 高橋俊彦

    第14回 回路とシステム軽井沢ワークショップ論文集   237 - 242   2001.4

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  • Floorplan Using a Tree Representation Reviewed

    P.-N.Guo, T.Takahashi, C.-K.Cheng, T.Yoshimura

    IEEE Trans. Computer-Aided Design   20 ( 2 )   281 - 289   2001.2

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    Language：English   Publishing type：Research paper (scientific journal)  

    DOI： 10.1109/43.908471

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  • A New Encoding Scheme for Rectangle Packing Problem Reviewed

    T.Takahashi

    Proc. Asia and South Pacific design Automation Conference 2000   200 - 203   2000.1

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  • Dropping method for rectangle packing problem Reviewed

    T Oshihiko, T Akahashi

    ISCAS 2000: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - PROCEEDINGS, VOL I   200 - 203   2000

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    Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

    In the rectangle packing problem, encoding schemes to represent the placements of rectangles are the key factors determining the efficiency of algorithms. SEQ-PAIR is one of the most sophisticated encoding scheme, which has been considered to have a small solution space [2]. In this paper, we begin with a packing procedure that does not look so smart. This procedure, however, leads us to another encoding scheme DS (the abbreviation for Dropping Schedule) whose solution space has the same size as that of SEQ-PAIR. Moreover, we introduce encoding scheme LOT as an adv ancedversion of DS, which has a smaller solution space.

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  • A Simple Encoding Scheme for Rectangle Packing Problem Reviewed

    T.Takahashi

    Proc. The 1999 International Technical Conference on Circuits/Systems   vol.1   352 - 354   1999.12

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  • A fast algorithm for routability testing Reviewed

    M Sarrafzadeh, T Takahashi

    ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 6   vol.6   178 - 181   1999

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    Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

    An L-shaped routing of a two-terminal net is its upper- or lower routing. Given a set of nets, the planar testability problem (PTP) is to decide if there exist a planar (i.e., pairwise non-crossing) L-shaped rotuing of all nets. PTP was solved via transformation to 2-satisfiability. Here, we propose an efficient greedy algorithm running in O(n(logn)(2), where n is the number of nets. The density-1 testability problem (D1TP) is to decide if there exists an L-shaped routing of all nets with density 1 (i.e., overlap routing is not allowed: however; routed may intersect each other). We extend-the PTP algorithm to solve the D1TP problem in O(nlogn) time.

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  • Balanced k-Coloring of a Set of Polyominos Reviewed

    TAKAHASHI Toshihiko

    91 - 96   1993

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  • Rearrangement Method of Dynamic Channel Assignment in Cellular Mobile System Reviewed

    K. Nakano, M. Sengoku, T. Takahashi, Y. Yamaguchi, S. Shinoda, T. Abe

    IEICE Trans. on Fundamentals   E75-A ( 12 )   1660 - 1666   1992.12

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  • Minimum Order of Unique-Center Graphs with Specified Radius and Diameter Reviewed

    T. Takahashi, K. Tochihara, C. Yamada, M. Sengoku, T. Abe, W. -K. Chen

    Proc. 1992 IEEE Asia-Pacific Conference on Circuits and Systems (APC-CAS1992)   1992.12

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  • 平面グラフの直線分描画の高さについて Reviewed

    高橋 俊彦

    情報処理学会論文誌   34 ( 9 )   1853 - 1858   1992.9

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  • Study on Optimal Graph Drawings Reviewed

    Tokyo Institute of Technology   1991.3

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    Language：Japanese   Publishing type：Doctoral thesis  

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  • 点位置が固定されたグラフの直交線分描画の線分数について Reviewed

    高橋俊彦, 梶谷洋司

    電子情報通信学会論文誌, 基礎・境界   J73-A ( 10 )   1654 - 1661   1990.10

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  • Minimum Rectilinear Drawing of a Graph whose vertices are Fixed on a Plane Reviewed

    Y. Kajitani, T. Takahashi

    Journal of Combinatorics, Information & System Sciences   15   233 - 246   1990

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  • Partition of a Set of Cells on a Floor with respect to Linear Adjacency Reviewed

    T. Takahashi, Y. Kajitani

    Proc. 1989 Joint Technical Conference on Circuits/Systems, Computers and Communications   527 - 530   1989.6

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  • The Noncross Matching and Applications to the 3-Side Switch Box Routing in VLSI Layout Design Reviewed

    Y. Kajitani, T. Takahashi

    Proc. 1986 IEEE International Symposium on Circuits and Systems (ISCAS1986)   776 - 779   1986

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Books

  • Algorithmic Aspects of VLSI Layout (Lecture Notes Series on Computing, Vol. 2)

    M. Sarrafzadeh, D. T. Lee（ Role： Contributor ,  The Virtual Dimensions of a Straight Line Embedding of a Plane Graph）

    World Scientific Publishing  1994.2 

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MISC

  • 方形パッキングの位相的表現(小特集 位相的パッキング表現とその応用 : 大規模問題を扱うための魔法の数々) Invited

    高橋 俊彦

    電子情報通信学会誌   98 ( 9 )   778 - 783   2015.9

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    Language：Japanese   Publishing type：Article, review, commentary, editorial, etc. (scientific journal)  

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  • Floorplanning using a tree representation: A summary

    T. Takahashi, P. N. Guo, C. K. Cheng, T. Yoshimura

    IEEE Circuits and Systems Magazine   3 ( 2 )   26 - 29   2003.6

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    Language：English   Publishing type：Article, review, commentary, editorial, etc. (other)   Publisher：IEEE Circuits and Systems Society  

    We present an ordered tree (O-tree) structure to represent nonslicing floorplans. The O-tree uses only n (2 + [lg n]) bits for a floorplan of n rectangular blocks. We define an admissible placement as a compacted placement in both X and y directions. For each admissible placement, we can find an O-tree representation. We show that the number of possible O-tree combinations is 0(n!2 2n-2/n 1.5). This is very concise compared to a sequence pair representation that has O((n!) 2) combina-tions. The approximate ratio of sequence pair and O-tree combinations is O(n 2(n/4e) n). The complexity of an O-tree is even smaller than a binary tree structure for a slicing floorplan that has O(n!2 5n-3/n 1.5) combinations. Given an O-tree, it takes only linear time to construct the placement and its constraint graph. We have developed a deterministic floorplanning algorithm utilizing the structure of O-tree. Empirical results on MCNC (www.mcnc.org) benchmarks show promising performance with average 16% improvement in wire length and 1% less dead space over the previous central processing unit (CPU) intensive cluster refinement method.

    DOI： 10.1109/MCAS.2003.1242834

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Presentations

  • 高速道路施設の効率的点検ルート

    高橋俊彦, 丸田航介

    電子情報通信学会技術報告, CAS2018-17, VLD2018-20, SIP2018-37, MSS2018-17  2018.6 

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  • 発見的な手法とバックトラック探索による被覆配列の生成

    佐藤俊輝, 高橋俊彦

    電子情報通信学会技術報告, CAS2017-54, MSS2017-38.  2017.11 

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  • 電子情報通信学会におけるグラフ理論に関する研究発表

    高橋 俊彦

    電子情報通信学会2017年総合大会講演論文集  2017.3 

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  • 高速道路設備の効率的点検ルート ～ Vehicle routing problemのバリエーション ～

    大塚拓実, 高橋俊彦

    電子情報通信学会技術報告, CAS2016-119, CS2016-80  2017.2 

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  • Colexicographic順序によるk-分木のz列に対するランキングおよびアンランキング

    明田川卓, 高橋俊彦

    電子情報通信学会技術報告, CAS2016-51, NLP2016-77  2016.10 

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  • ビットの照合順序を考慮したトライによるパケット分類法の高速化

    小林由人, 高橋俊彦, 三河賢治, 田中賢

    電子情報通信学会2016年総合大会講演論文集B-7-27  2016.3 

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  • ビットの照合順序を考慮したトライに基づくパケット分類手法

    小林由人, 高橋俊彦, 三河賢治, 田中賢

    電子情報通信学会技術報告, CAS2015-53, MSS2015-27  2015.11 

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  • トライを用いた高速パケット分類法の提案

    小林由人, 高橋俊彦, 三河賢治, 田中 賢

    電子情報通信学会2015年総合大会講演論文集B-7-48  2015.2 

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  • p6タイリング可能なポリアモンドの列挙索引化

    野澤友暉, 高橋俊彦

    電子情報通信学会技術報告, CAS2014-54, NLP2014-48  2014.10 

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  • おねえさんの問題のパス数の桁は格子サイズに比例して増加する

    高橋 俊彦

    電子情報通信学会2014年ソサイエティ大会講演論文集A-1-9  2014.9 

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  • キャタピラ上のグラフ・シェアリング・ゲーム International conference

    高橋俊彦, 佐藤拓哉

    情報科学技術フォーラム(FIT2014) A-024  2014.9 

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  • Baxter Permutationの列挙

    清水創介, 高橋俊彦

    電子情報通信学会 回路とシステム研究会（CAS）  2013.1  電子情報通信学会

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    Language：English   Presentation type：Oral presentation (general)  

    Venue：別府国際コンベンションセンター  

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  • Slicing Floorplanに対するZDD (Sequence BDD)の構築

    清水創介, 高橋俊彦

    電子情報通信学会技術報告, CAS2012-65  2013.1 

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    Language：Japanese   Presentation type：Oral presentation (general)  

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  • Representation of a Box Partitioned by Rectangles

    Toshihiko Takahashi

    2012.9 

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    Language：Japanese   Presentation type：Oral presentation (general)  

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  • (3n-4)-bit Representation of Rectangular Partitions

    Toshihiko Takahashi

    2012.3 

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    Language：Japanese   Presentation type：Oral presentation (general)  

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  • A Recurrence for the Number of Baxter Permutations via Rectangular Partition

    Toshihiko Takahashi

    2011.11 

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  • Enumeration of Slicing floorplan

    Shunichi Echizen, Toshihiko Takahashi

    2011.9 

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  • On pruning rules in optmal algorithms for the minimum rectilinear Steiner arborescence problem II

    Masayuki Nagase, Toshihiko Takahashi

    2011.3 

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  • On pruning rules in exact algorithms for the minimum rectilinear Steiner arborescence problem

    Masayuki Nagase, Toshihiko Takahashi

    2010.11 

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  • The simplest and smallest network on which the Ford-Fulkerson maximum flow procedure may fail to terminate

    Toshihiko Takahashi

    2010.11 

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  • Schroder Pathの列挙

    越前俊一, 高橋俊彦

    電子情報通信学会2010ソサイエティ大会  2010.9 

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  • RaoのRectilinear Steiner Arborescenceアルゴリズムにおける摂動の効果II

    山田拓也, 高橋俊彦

    電子情報通信学会ソサイエティ大会  2010.8 

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    Language：Japanese   Presentation type：Oral presentation (general)  

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  • Permutation Representation of Stacked Rectangular Drawings

    Toshihiko Takahashi

    2010.3 

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    Language：Japanese   Presentation type：Poster presentation  

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  • Effects of Perturbations in Rao's Rectilinear Steiner Arborescence Algorithm

    Toshihiko Takahashi

    2010.1 

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  • Coding Floorplans with Far Fewer Bits International conference

    T. Takahashi, R. Fujimaki, Y. Inoue

    2009年 日台半導体設計自動化科学技術研究シンポジウム  2009.9  公立大学法人北九州市立大学国際環境学部集積システム設計環境開発研究センター

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    Language：English   Presentation type：Oral presentation (invited, special)  

    Venue：北九州市立大学  

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  • An O(n log n)-time algorithm solving square sub-crossbar problem for two-directional orthogonal rays

    高橋俊彦

    電子情報通信学会2009年総合大会  2009.3  電子情報通信学会

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    Language：Japanese   Presentation type：Oral presentation (general)  

    Venue：愛媛大学  

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  • (4n-3)-bit representation of rectangular drawings or floorplans

    Toshihiko Takahashi

    2008.11 

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  • An asymptotic estimate of the numbers of rectangular drawings or floorplans

    Ryo Fujimaki, Youhei Inoue, Toshihiko Takahashi

    2008.6 

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  • Finding a longest common subsequence of two twistable sequences

    Youhei Inoue, Toshihiko Takahashi

    2007.11 

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  • 多端子ネット配線の配線長と混雑度の最小化手法

    高橋俊彦, 芳賀雅洋

    電子情報通信学会技術報告, CAS2006-53,  2006.11 

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  • 矩形迷路のパス決定アルゴリズム

    高橋俊彦, 久住 淳

    電子情報通信学会技術報告, CAS2005-57, CST2005-26  2005.11 

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  • レクトリニア多角形パッキングのO-Tree表現

    高橋 俊彦

    電子情報通信学会2003ソサイエティ大会講演論文集A-1-21  2003.9 

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  • O-Treeを用いたレクトリニア多角形パッキングアルゴリズム

    高橋俊彦, 西片健也, 高橋勇祐

    情報処理学会第65回全国大会, 4G-6, Vol.1  2003.3 

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  • 矩形パッキングのための最大重み減少列を求めるアルゴリズム

    高橋 俊彦

    電子情報通信学会技術研究報告, VLSI設計技術 96(201)  1996.7 

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  • 指定された半径と直径を持つ唯一の中心を持つグラフの最小点数

    高橋俊彦, 田村裕, 栃原謙, 山田千枝子, 仙石正和, 阿部武雄, Wai-Kai Chen

    電子情報通信学会技術報告, CAS92-50  1992.9 

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  • フローネットワークにおける被服問題に関する一研究

    川上博, 田村裕, 仙石正和, 高橋俊彦, 山口芳雄

    電子情報通信学会技術報告, CAS92-53  1992.9 

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  • 平面グラフの直線分描画の高さ

    高橋 俊彦

    電子情報通信学会技術報告, COMP90-30  1990.9 

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  • グラフの最小線分数による直交線分描画

    梶谷洋司, 高橋俊彦

    情報処理学会研究報告, アルゴリズム(AL) 1-4  1988.5 

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  • グラフの直交線分による最適描画について

    梶谷洋司, 高橋俊彦

    電子情報通信学会技術報告, CAS87-204  1987.12 

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  • 非交差マッチングと端子が可動である3辺スイッチボックスの最小面積配線

    梶谷洋司, 高橋俊彦

    電子通信学会技術報告, CAS85-85  1985.10 

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Awards

  • 2002 IEEE Circuits and Systems CAD Transactions Best Paper Award

    2002.6  

    Pei-Ning Guo, Toshihiko Takahashi, Chung-Kuan Cheng, Takeshi Yoshimura

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    Award type：Honored in official journal of a scientific society, scientific journal  Country：United States

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Research Projects

  • 3次元フロアプランの符号化と数理

    2010.4 - 2013.3

    System name：科学研究費助成事業

    Research category：基盤研究(C)

    Awarding organization：日本学術振興会

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    Grant type：Competitive

    VLSI の高集積化、微細化により、1チップ内に詰め込まれるゲートの数は億単位となった。それでもなお、回路規模に対する要求は高まり、これまで平面(2次元)上で設計されていたレイアウトも、もはや3 次元的に行わなければならないことが認識され始めた。
    2次元レイアウト設計ですら、人手による設計が困難となって久しい。まして、3次元レイアウト設計ではなおさらである。
    レイアウト設計の自動化には、その基盤となるレイアウトの数理が欠かせない。2次元レイアウトに対しては、過去数十年の間に多くの研究がなされ、その結果として幾つかの実用的なレイアウトアルゴリズムが開発されてきた。
    3次元レイアウトは、製造技術もまだ新しいため、モデル化も含めその性質がよくわかっていない。
    本研究は特に3次元フロアプランに対する数理的基盤を与え、レイアウトアルゴリズムの開発に貢献することを目的とする。

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Other research activities

  • 知識ベース・知識の森

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    電子情報通信学会がカバーする分野の技術・知識をまとめた電子情報通信ハンドブックのデータベース版．執筆分は12群 電子情報通信基礎, 2編 離散数学のうち, 全体概要(上野修一, 高橋俊彦,松林昭, 2014年1月受領), 1章 基礎(高橋俊彦, 2009年9月受領), 3章 グラフ理論(高橋俊彦, 2011年7月受領).
    http://www.ieice-hbkb.org/portal/doc_index.html

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Teaching Experience (researchmap)

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Teaching Experience

  • 論理回路

    2022
    Institution name：新潟大学

  • アルゴリズム特論

    2021
    Institution name：新潟大学

  • 研究室体験実習

    2021
    Institution name：新潟大学

  • 工学リテラシー入門(情報電子分野)

    2017
    Institution name：新潟大学

  • 知能情報システム概論

    2017
    Institution name：新潟大学

  • 情報システム構成論

    2016
    -
    2018
    Institution name：新潟大学

  • 情報工学文献詳読Ⅰ

    2013
    -
    2015
    Institution name：新潟大学

  • 情報工学研究発表(外部発表)

    2013
    -
    2015
    Institution name：新潟大学

  • 情報工学セミナーⅠ

    2013
    -
    2015
    Institution name：新潟大学

  • 情報工学セミナーⅡ

    2013
    -
    2015
    Institution name：新潟大学

  • 情報工学特定研究Ⅱ

    2013
    -
    2015
    Institution name：新潟大学

  • 情報工学発表演習(中間発表)

    2013
    -
    2015
    Institution name：新潟大学

  • 情報工学特定研究Ⅰ

    2013
    -
    2015
    Institution name：新潟大学

  • 自然科学総論Ⅲ

    2011
    -
    2020
    Institution name：新潟大学

  • 情報機器操作入門

    2010
    Institution name：新潟大学

  • 情報数理演習III

    2008
    Institution name：新潟大学

  • 形式言語とオートマトン

    2008
    Institution name：新潟大学

  • 離散数学

    2007
    Institution name：新潟大学

  • 組合せアルゴリズム特論

    2007
    Institution name：新潟大学

  • データ構造とアルゴリズム

    2007
    Institution name：新潟大学

  • 情報数理演習I

    2007
    -
    2021
    Institution name：新潟大学

  • 情報数理演習II

    2007
    -
    2021
    Institution name：新潟大学

  • 情報数理基礎演習

    2007
    -
    2017
    Institution name：新潟大学

  • アルゴリズム特論

    2007
    -
    2014
    Institution name：新潟大学

  • 情報工学実験I

    2007
    -
    2009
    Institution name：新潟大学

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